`timescale 1ns/1ps
`default_nettype none

/* NOTE:
* - 本模块用于存放1行逐点调整数据
* - 使用altera ip会使用4个M9K，手写rtl可以节省一个
*/

module ram_768x32 (
    input  wire         I_wclk,
    input  wire         I_wren,
    input  wire [9:0]   I_wraddr,
    input  wire [31:0]  I_data,
    input  wire         I_rclk,
    input  wire         I_rden,
    input  wire [9:0]   I_rdaddr,
    output wire [31:0]  O_q
);
//------------------------Parameter----------------------

//------------------------Local signal-------------------
wire [31:0] ram0_q;
wire [31:0] ram1_q;
wire [31:0] ram2_q;
reg  [2:0]  rd_sel;

//------------------------Instantiation------------------
//ram_256x32
ram_256x32 ram0 (/*{{{*/
    .wrclock   ( I_wclk ),
    .wren      ( I_wren && I_wraddr[9:8] == 2'd0 ),
    .wraddress ( I_wraddr[7:0] ),
    .data      ( I_data ),
    .rdclock   ( I_rclk ),
    .rden      ( I_rden ),
    .rdaddress ( I_rdaddr[7:0] ),
    .q         ( ram0_q )
);/*}}}*/

//ram_256x32
ram_256x32 ram1 (/*{{{*/
    .wrclock   ( I_wclk ),
    .wren      ( I_wren && I_wraddr[9:8] == 2'd1 ),
    .wraddress ( I_wraddr[7:0] ),
    .data      ( I_data ),
    .rdclock   ( I_rclk ),
    .rden      ( I_rden ),
    .rdaddress ( I_rdaddr[7:0] ),
    .q         ( ram1_q )
);/*}}}*/

//ram_256x32
ram_256x32 ram2 (/*{{{*/
    .wrclock   ( I_wclk ),
    .wren      ( I_wren && I_wraddr[9:8] == 2'd2 ),
    .wraddress ( I_wraddr[7:0] ),
    .data      ( I_data ),
    .rdclock   ( I_rclk ),
    .rden      ( I_rden ),
    .rdaddress ( I_rdaddr[7:0] ),
    .q         ( ram2_q )
);/*}}}*/

//------------------------Body---------------------------
assign O_q = rd_sel[0]? ram0_q
           : rd_sel[1]? ram1_q
           : ram2_q;

// rd_sel
always @(posedge I_rclk) begin
    if (I_rden) begin
        case (I_rdaddr[9:8])
            2'd0: rd_sel <= 3'b001;
            2'd1: rd_sel <= 3'b010;
            2'd2: rd_sel <= 3'b100;
            2'd3: rd_sel <= 3'b000;
        endcase
    end
end

endmodule

`default_nettype wire

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